1. Field of the Invention
The present invention relates to an interrupt controller that lets a microprocessor flexibly process various interrupt requests in the descending order of priorities of the interrupt requests.
2. Description of the Prior Art
A microprocessor with an interrupt function generally executes external and internal interrupt requests in the predetermined order of priorities of the interrupt requests.
FIG. 1 shows an interrupt controlling system according to a prior art. An interrupt controller 71 outputs an interrupt level signal I to a microprocessor 72 to request the microprocessor to process the interrupt request. If a priority of the interrupt level signal I is lower than an acceptable priority set in an internal register (not shown) of the microprocessor 72, the microprocessor 72 does not process data related to the interrupt level signal I but puts the interrupt request in queue.
In this way, once an interrupt level signal corresponding to an interrupt request is outputted from the conventional interrupt controlling system to a microprocessor, this interrupt level signal is queued until the corresponding interrupt request is accepted by the microprocessor. Therefore, if another interrupt request that has a higher priority than that of the queued interrupt request occurs, the latter interrupt request of higher priority cannot be outputted to the microprocessor.
Namely, even if the latter interrupt request is accepted by the microprocessor, this interrupt request is forcibly queued because the previously occurred interrupt request has not been accepted by the microprocessor due to its low priority and queued.